1. Field of the Invention
The present invention generally relates to testing of integrated circuits and, more specifically, to the diagnosis of detected faults in integrated circuits.
2. Description of Related Art
Testing of integrated circuits is well known in the art. When a manufactured chip fails testing, it is often desirable to diagnose the source of the failure. The need to diagnose such failures is driven by design debug and/or yield improvement. In a typical design debug scenario, almost every chip fails testing. Diagnosis is needed to identify the source of a failure, which is often either a design error or an oversight which results in a timing error, or a database that has not been updated after an engineering change order (ECO). The chip is not yet in volume production, and tester time or server time required for diagnosis are not critical.
Yield improvement relates to a chip which is in production. A subset of manufactured chips fail testing, resulting in reduced yield. In a high volume chip, a lower yield has a significant impact on cost. Identifying failure sources may enable changes to a design that will reduce the frequency of these failures, thereby increasing yield and reducing the cost of manufacturing good devices.
In both cases, the diagnostic data needed from the tester is identical: failing vectors need to be identified, and, for each failing vector, failing flops need to be identified. Once data has been gathered, it can then be analyzed to diagnose failures down to a gate, to help debug the design or improve yield. In both design debug and yield improvement modes, the analysis can be done off-line. Narrowing the diagnosis from failing flops down to a failing gate presents several challenges.
Diagnosis requires comparing observed failing output to simulated failures of modeled faults. Since actual defects do not always correspond to a modeled fault, a perfect match cannot always be found between observed failures and simulated faulty behavior. Fault simulation usually uses a single fault model, i.e., it assumes at most one fault is present in the circuit at a time. In practice, a failing device may have more than one defect. As a result, it is difficult to match single fault simulations to observed failing data.
In the past, sign-off of a chip with gate-level diagnosis capability required the building of a fault dictionary. Diagnosis would consist of searching the fault dictionary for a match with the observed failing data. It is now well established that such an approach is no longer viable, as the size of the dictionary is prohibitive for chips now designed and manufactured. Instead, it is preferred to perform diagnosis dynamically using observed failing data as input to diagnostic fault simulation.
A Song et al. paper entitled “Diagnostic for the IBM S/390 600 MHz G5 Microprocessor”, published in the 1999 ITC Proceedings describes a software based diagnostic technique which involves applying test patterns to a circuit using a tester and identifying latches/pins that fail. After identifying fault candidates, each fault is simulated by injecting the fault into a simulator. The tester results and simulation results are used to determine a diagnostic score for each fault candidate. The score is a composite of the number of outputs which failed on a tester but passed in simulation, the number of outputs which failed both in the tester and in simulation, and the number of outputs which passed on the tester but failed in simulation.
De and Gunda in a paper entitled “Failure Analysis for Full-Scan Circuits, 1995 ITC Proceedings, p. 636–645, propose a method which employs a metric based on match/mismatch ratios. The proposal ignores outputs where there is a discrepancy between an observed fault effect and a fault candidate fault-effect and propose coefficients to weigh the match and mismatch. The authors admit that the method does not work well when a defect is not a “stuck-at” defect. The patentee asserts that a unique signature for each fault is desirable. The proposed method requires modification of Automatic test pattern generation (ATPG) methods to accommodate the method. Another drawback of the method is that it requires layout information, which may not always be available, and explicit analysis of the shorts.
Ferguson et al. U.S. Pat. No. 6,202,181 granted on Mar. 13, 2001 for “Method for Diagnosing Bridging Faults in Integrated Circuits” proposes a method for diagnosing bridging faults using stuck-at signatures. The method considers as candidates only those faults which are determined to be realistic through an inductive fault analysis. The method imposes match restrictions and match requirements during matching in order to minimize diagnosis size. Match ranking is applied and the matching criteria relaxed to increase the effective precision and to increase the number of correct diagnoses. The method reduces the number of bridging fault candidates by constructing a dictionary of composite signatures of node pairs based on a ranking threshold.
Shimono U.S. Pat. No. 6,308,293 granted on Oct. 23, 2001 for “Fault Diagnosis Apparatus and Recording Medium with a Fault Diagnosis Program Recorded Thereon” provides a fault diagnosis apparatus which estimates a disconnection fault site intermediate of a branch wiring line in an LSI based on a result of an LSI test performed by using a test pattern. An indefinite value simulation narrowing down section uses a test pattern to perform, for each gate included in a suspected fault gate set, a simulation in which the output value of the gate is set to an indefinite value, and removes any gate from which a definite value is outputted among those outputs which have been determined to be errors with error test patterns. An output value check narrowing down section removes any gate from a suspected fault gate set if the gate satisfies a condition that the output value thereof at least in one error test pattern is different from that in the other error test patterns. A branch destination fault simulation narrowing down section defines 0/1 stuck-at faults to output branch designations of each gate included in the suspected fault gate set and performs a logic simulation using the test pattern. The branch destination fault simulation narrowing down section removes any gate from the suspected fault gate set if the gate does not have an output branch destination fault which is not detected at a normal output but is detected at an error output. The patent discloses a well known method of generating an initial fault candidate list is by simply considering the fanin of outputs with at least one observed fault effect.